module ALU (
	input [31:0] reg_data_1,
	input [31:0] reg_data_2,

	input [3:0] opcode,

	output reg [31:0] alu_result,
	output isEqual

);
	wire signed [31:0] reg_data_1_signed;
	wire signed [31:0] reg_data_2_signed;

	assign isEqual = reg_data_1_signed == reg_data_2_signed;

	always @ (*) begin
		case (opcode) 
		    0: alu_result = reg_data_1 + reg_data_2;
		    1: alu_result = reg_data_1 - reg_data_2;
		    2: alu_result = reg_data_1 & reg_data_2;
		    3: alu_result = reg_data_1 | reg_data_2;
		    4: alu_result = reg_data_1 ^ reg_data_2;
		    5: alu_result = reg_data_1 << reg_data_2;
		    6: alu_result = reg_data_1 >> reg_data_2;
		    7: alu_result = reg_data_1_signed >>> reg_data_2;
		    8: alu_result = (reg_data_1_signed < reg_data_2_signed )? 1: 0;
		    9: alu_result = (reg_data_1 < reg_data_2 )? 1: 0;
		    default: alu_result = 'b0;  
		endcase
	end
endmodule
